Semiconductor test apparatus

ABSTRACT

There is disclosed a semiconductor test apparatus enabling writing into an information write space of a block including a failure cell into which block writing is inhibited partially or entirely by the bad block mask function and the fail loop back function. A pattern generation block outputs to an output controller a release signal (S 4 ) for releasing the write inhibit instruction defined by an inhibit signal (S 3 ) and a mask signal (SI). When the output controller receives the release signal (S 4 ), the output controller outputs a write enable signal (WE) to an MUT ( 4 ).

TECHNICAL FIELD

The present invention relates to a semiconductor test apparatus whichtests a memory device such as a flash memory as a device under test, andmore particularly to a semiconductor test apparatus having a bad blockmask (BBM) function and a fail loop back (FLB) function.

BACKGROUND ART

A semiconductor test apparatus which tests a flash memory or the like asa device under test inputs a test pattern signal to a memory device, andcompares a response output signal from the memory device with anexpected pattern signal. Further, it detects a mismatch in a comparisonresult as a failure of a memory cell, and stores failure information(fail data) in a failure analysis memory. In the failure analysis memoryis set the same address space as that in the memory device and storedfailure information at the same address as an address of a failure cell.

An example of a conventional semiconductor test apparatus will now bebriefly described with reference to FIG. 5.

As shown in FIG. 5, the conventional semiconductor test apparatus isconstituted by a pattern generation block 1, a waveform formatter/timinggenerator 2, an output controller 3, a logic comparator 5, and a failureanalysis memory 6.

The pattern generation block 1 generates a cycle signal, a waveformcontrol signal and an expected pattern signal as well as an addresssignal which specifies a write address in a memory device (MUT: Memorydevice Under Test) 4.

Further, the waveform formatter/timing generator 2 outputs a testpattern signal whose waveform is formatted by the waveform controlsignal, and also outputs a write enable signal which enables writing ofthe test pattern signal into the memory device.

It is to be noted that an illustration of a transmission path of theexpected pattern signal is omitted in FIG. 5.

Furthermore, the logic comparator 5 compares an output signal outputtedfrom the memory device 4 in response to the input test pattern signalwith an expected pattern signal. It detects as a failure cell a mismatchresult of the comparison between the expected pattern signal and theresponse output signal. When the failure cell is detected, the logiccomparator 5 outputs a fail signal S2 to a failure analysis memory 6.

The failure analysis memory 6 having the fail signal S2 inputted theretostores failure information at an address indicated by an address signal.

Meanwhile, in case of testing as a device under test a memory devicesuch as a flash memory in which a memory area is divided into aplurality of blocks, writing information into a part or all of the blockincluding a failure cell is inhibited by a bad block mask function or afail loop back function.

The bad block mask function and the fail lop back function will now bebriefly described with reference to FIG. 6. FIG. 6 typically shows anaddress space of the memory device. In an example depicted in FIG. 6, amemory area of the memory device is divided into a plurality of blocks.Furthermore, each block is constituted by a memory logic address spacein which data or the like is written and an information write spacewhich is a redundant space.

The bad block mask function is a function which inhibits writinginformation into a block in which a failure cell is detected in advanceby a pre-check or the like. Information of the previously detectedfailure cell (failure information) is held in the failure analysismemory 6. The failure analysis memory 6 outputs a mask signal S1 whichinhibits writing in the entire block including that failure cell basedon this failure information.

Based on this mask signal S1, writing in an entire area of a secondblock 42 in the address space depicted in FIG. 6 is inhibited. Thiswrite inhibit area also includes an information write space 42 a.

Moreover, the fail loop back (FLB) function is a function which inhibitswriting into a memory area which is tested after a failure cell in ablock including that failure cell when the logic comparator 5 detectsthe failure cell. The logic comparator 5 which has detected the failurecell outputs a fail signal S2 to the failure analysis memory 6, and alsooutputs an inhibit signal S3 which inhibits writing into a memory areawhich is tested after a newly detected failure cell in a block includingthat failure cell.

Based on this inhibit signal S3, in the address space depicted in FIG.6, writing into an area after a failure generation address 400 indicatedby “f” in a fourth block 44 is inhibited. This inhibit area alsoincludes a part 44 a of the information write space.

Incidentally, when again testing the same memory device 4, writing intothe entire fourth block 44 including the failure cell is inhibited bythe mask signal S1.

Additionally, when one or both of the inhibit signal S3 and the masksignal S1 are inputted, the output controller 3 a stops outputting ofthe write enable signal (WE) to the memory device. In order to realizethis function, in the conventional example, the output controller 3 a isconstituted by a first OR circuit 31, a second OR circuit 32 and aflip-flop 30.

The inhibit signal S3 and the mask signal S2 are inputted to the firstOR circuit 31. Further, an output from the first OR circuit 31 and atiming signal from the waveform formatter/timing generator 2 areinputted to the second OR circuit 32. Furthermore, an output of thesecond OR circuit 32 is inputted to the flip-flop 30 as a reset signalS5, and the write enable signal (WE) is inputted to the same as a setsignal.

As a result, when at least one of the inhibit signal S3 and the masksignal S1 is outputted to the first OR circuit 31, a reset signal S5 isinputted to the flip-flop 30, and output of the write enable signal (WE)is stopped. In this manner, writing into a block in which a failure cellis detected in advance or a remaining part of a block in which a failurecell is newly detected during the test is inhibited.

Meanwhile, a redundant space is generally provided in an address spaceof a memory area of, e.g., a flash memory, and this redundant space isused as an information write space. For example, a flag indicating thata failure cell is included may be written into the information writespace of a block in which a failure cell is detected in some cases.Writing the flag in this manner can readily grasp the block includingthe failure cell.

However, when writing into a part or all of the block including thefailure cell is inhibited by the back block mask function or the failloop back function, writing of a flag or the like into the informationwrite space of such a block is also inhibited. As a result, a writecycle required to write information into the information write spacemust be added, which generates a problem that processing takes time.

In order to solve the above-described problems, it is therefore anobject of the present invention to provide a technique which enableswriting information into an information write space of a block includinga failure cell, writing into a part or all of which block is inhibitedby a bad block mask function or a fail loop back function.

DISCLOSURE OF THE INVENTION

According to the present invention, there is provided a semiconductortest apparatus which tests as a device under test a memory device whosememory area is divided into a plurality of blocks, comprising: a patterngeneration block which generates a waveform control signal and anexpected pattern signal as well as an address signal specifying a writeaddress in the memory device; a waveform formatter/timing generatorwhich outputs a test pattern signal whose waveform is formatted by thewaveform control signal and also outputs a write enable signal whichenables writing of the test pattern signal into the memory device; alogic comparator which compares an output signal outputted from thememory device in response to the input test pattern signal with anexpected pattern signal, detects a failure cell based on a mismatch ofthe expected pattern signal and the response output signal and outputs afail signal, and also outputs an inhibit signal which instructsinhibition of writing into a memory area which is tested after thefailure cell in a block in which the failure cell is detected; a failureanalysis memory which stores failure information at an address indicatedby the address signal, and outputs a mask signal which instructsinhibition of writing into the block in which the failure cell isdetected in advance; and an output controller which stops output of thewrite enable signal to the memory device when one or both of theinhibition signal and the mask signal are inputted, wherein the patterngeneration block outputs a release signal which cancels the writeinhibit instruction based on the inhibit signal and on the mask signal,and output controller outputs the write enable signal when the releasesignal is inputted even if one or both of the inhibit signal and themask signal are inputted.

According to such a semiconductor test apparatus of the presentinvention, write inhibit processing to the block by the bad block maskfunction or the fail loop back function can be released by the releasesignal. As a result, information of, e.g., a flag can be written intothe information write space of the block in which writing of informationis inhibited. Consequently, the information write space can beeffectively used.

Further, according to the semiconductor test apparatus of the presentinvention, the pattern generation block outputs the release signal witha timing to write information into the cell in the information writespace of the block that writing is inhibited by the mask signal and/or atiming to write information into the cell in the write area included inan area in which writing is inhibited by the inhibit signal.

Outputting the release signal with such a timing enables writingarbitrary information such as a flag indicating that a failure cell isincluded into the information write space which is a redundant space ofthe block in which writing is inhibited.

Furthermore, according to the semiconductor test apparatus of thepresent invention, the output controller includes an OR circuit to whichthe inhibit signal and the mask signal are inputted, an AND circuit towhich an output from the OR circuit and the release signal are inputted,and a flip-flop to which an output from the AND circuit is inputted as areset signal and the write enable signal is inputted as a set signal.

In cases where the output controller adopts such a structure, even ifone or both of the inhibit signal and the mask signal are outputted, thewrite instruction signal can be inputted to the memory device when therelease signal is outputted.

Moreover, according to the semiconductor test apparatus of the presentinvention, the memory device is a flash memory. That is, the presentinvention is particularly suitable for use in a test of a flash memory.

Additionally, according to the semiconductor test apparatus of thepresent invention, the release signal is included in a memory devicecontrol signal.

With such a structure, using the memory control signal can readilygenerate the release signal with a timing of a write pattern inputted tothe memory device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a structure of a semiconductortest apparatus according to the present invention;

FIG. 2 is a type drawing illustrating a write inhibit area of a memoryaccording to an embodiment of the present invention;

FIG. 3 is a timing chart illustrating an operation of an outputcontroller of the semiconductor test apparatus according to the presentinvention;

FIG. 4 is a type drawing illustrating an access order in a memory as adevice under test;

FIG. 5 is a block diagram illustrating a structure of a conventionalsemiconductor test apparatus; and

FIG. 6 is a type drawing illustrating a write inhibit area of a memoryin a prior art.

BEST MODE FOR CARRYING OUT THE INVENTION

The present invention will now be described in detail hereinafter withreference to the accompanying drawings.

First, referring to FIG. 1, a structure of a semiconductor testapparatus according to an embodiment will be explained.

This semiconductor test apparatus tests a flash memory (MUT: Memorydevice Under Test) 4 whose memory area is divided into a plurality ofblocks as a device under test, and it is constituted by a patterngeneration block 1, a waveform formatter/timing generator 2, an outputcontroller 3, a logic comparator 5 and a failure analysis memory 6 asshown in FIG. 1.

It is to be noted that illustrations and explanations of a delaycircuit, a pin electronics and others usually included in thesemiconductor test apparatus are omitted in this embodiment.

The pattern generation block 1 generates a cycle signal, a waveformcontrol signal and an expected pattern signal as well as an addresssignal specifying a write address in the memory device 4.

It is to be noted that the illustration of a transmission path of theexpected pattern signal is omitted in FIG. 1.

Moreover, the pattern generation block 1 outputs a release signal S4which cancels the write inhibit instruction based on an inhibit signalS3 and on a mask signal s1 which will be described later. The releasesignal S4 is included in a memory device control signal. This releasesignal S4 is outputted with a timing that information is written into acell in an information write space of a block in which writing isinhibited by the mask signal S1 and/or a timing that information iswritten into a cell in a write area included in an area in which writingis inhibited by the inhibit signal S3.

The waveform formatter/timing generator 2 outputs a test pattern signalwhose waveform is formatted by the waveform control signal, and alsooutputs a write enable signal (WE) which enables writing of the testpattern signal into the memory device 4.

The logic comparator 5 compares an output signal outputted from thememory device in response to the input test pattern signal with anexpected pattern signal, and detects a failure cell based on a mismatchof the expected pattern signal and the response output signal, therebyoutputting a fail signal. It also outputs an inhibit signal whichinstructs inhibition of writing into a memory area which is tested aftera failure cell in the block in which this failure cell is detected.

The failure analysis memory 6 stores failure information at an addressindicated by the address signal, and outputs a mask signal whichinstructs inhibition of writing information into the block in which afailure cell is detected in advance.

Additionally, when one or both of the inhibit signal S3 and the masksignal S1 are inputted, the output controller 3 stops output of thewrite enable signal (WE) to the memory device in principle.

However, even if one or both of the inhibit signal S3 and the masksignal S1 are inputted, the output controller 3 outputs the write enablesignal (WE) when the release signal S4 is inputted.

In order to realize such a function, the output controller 3 isconstituted by a flip-flop 30, a first OR circuit 31, a second ORcircuit 32 and an AND circuit 33.

The inhibit signal S3 and the mask signal S1 are inputted to the firstOR signal 31. Further, an output from the first OR circuit 31 and therelease signal S4 are inputted to the AND circuit 33. Furthermore, anoutput from the AND circuit 33 and a timing signal outputted from thewaveform formatter/timing generator 2 are inputted to the second ORcircuit 32. Moreover, an output from the second OR circuit 32 isinputted to the flip-flop 30 as a reset signal S5.

A control example when writing into an address space depicted in FIG. 2is carried out will now be described with reference to a timing chart ofFIG. 3.

The address space of the memory device illustrated in FIG. 2 is dividedin to a plurality of blocks (41, 42, 43, . . . ) like one shown in FIG.6. Each block is constituted by a memory logic address space into whichdata or the like is written and an information write space which is aredundant space.

Additionally, in the address space depicted in FIG. 2, writinginformation into an entire second block 42 is inhibited by a bad blockmask (BBM) function. Further, since a failure indicated by “f” isdetected at a failure generation address 400 in a fourth block, writinginformation into this block is partially inhibited by a fail loop back(FLB) function.

In this embodiment, a flag indicative of a block including a failurecell is written into each of the information write space of the secondblock in which writing information is inhibited by the BBM function andthe information write space of the fourth block in which writinginformation is inhibited by the FLB function. Therefore, in thisembodiment, the write inhibit state is temporarily released by therelease signal.

The timing chart of FIG. 3 shows output timings of the mask signal S1and the inhibit signal S3 inputted to the output controller 3, the resetsignal S4 outputted from the output controller 3 and the fail signal S2.Here, a state that a value of each signal is “1” is determined as anoutput state.

Output timings of the respective signals will now be sequentiallydescribed in accordance with each block.

<1> First Block

First, both of the mask signal S1 and the inhibit signal S3 are notoutputted in a first block write period. That is, values of the masksignal S1 and the inhibit signal S3 remain as “0”. Therefore, an outputvalue of the first OR circuit 31 of the output controller 3 is also “0”.

Furthermore, the release signal S4 is output by an instruction of aprogram during the first block write period. That is, a value of therelease signal S4 temporarily becomes “1”. As a result, the output value“0” of the first circuit 31 and an inverted value “0” of the releasesignal S4 are inputted to the AND circuit 33 of the output controller 3,but an output value of the AND circuit 33 becomes “0”.

Moreover, a timing signal from the waveform formatter/timing generator 2and the output value “0”of the AND circuit 33 are inputted to the secondOR circuit 32 of the output controller 3. Therefore, a value of thereset signal S5 outputted from the second OR circuit 32 becomes “0”irrespective of a value of the timing signal.

When a value of the reset signal S5 is not outputted, i.e., in a periodthat a value of the reset signal S5 is “0”, writing is not inhibited.Therefore, the flip-flop 30 outputs the write signal outputted from thewaveform formatter/timing generator 2 and the test pattern signalincluding the write enable signal (WE) to the memory device (MUT) 4.

<2> Second Block

In the second block, a failure cell has been already detected by apre-check or the like. Therefore, in a second block write period, thefailure analysis memory 6 outputs the mask signal S1 to the outputcontroller 3 by the bad block mask (BBM) function. That is, a value ofthe mask signal S1 becomes “1”. Therefore, an output value of the firstOR circuit 31 of the output controller 3 also becomes “1”.

As a result, when a value of the release signal S4 is “0”, an outputvalue of the AND circuit 33 becomes “1”, and a value of the reset signalS5 outputted from the second OR circuit 32 becomes “1”. Therefore, adriver output from the flip-flop 30 is stopped, and writing informationinto the memory device 4 is inhibited.

In this manner, in a period that the release signal S4 is not outputted,the second block 42 enters the write inhibit state by the bad block mask(BBM) function.

In this embodiment, a flag 401 indicated by “F” in FIG. 2 is writteninto an information write area 42 a of the second block 42 in whichwriting information is inhibited. Therefore, the release signal S4 isoutputted with a timing that this flag 401 is written. That is, a valueof the release signal S4 is set to “1”. The release signal S4 isoutputted as a memory device control signal (MUT control signal) “C0”.In a period that the value of the release signal S4 is “1”, an outputvalue of the AND circuit 33 becomes “0”, and a value of the reset signalS4 outputted from the second OR circuit 32 becomes “0”.

An example of a data write pattern into the memory device 4 will now betypically described with reference to FIG. 4.

Areas X=0 to 2 in the address space depicted in FIG. 4 correspond to thememory logic address space shown in FIG. 2, and areas X=3 correspond tothe information write space shown in FIG. 2. Here, a description will begiven regarding Y=0 to 3 in the address space shown in FIG. 4 as thesecond block for the convenience's sake.

As data write patterns, examples of (1) of an initial setting pattern ofa register and (2) an execution command pattern are given. The datawrite pattern instructs writing data in the order indicated by arrowsshown in FIG. 4.

(1) Initial Setting Pattern

-   LMAX=#3-   XT=#4-   YT=#3-   IDX8=#C-   EXTRA WRITE=C0-   CPE=R

“LMAX=#3” in the initial setting pattern indicates that a maximum valueof an X address is “#3”. Further, “XT=#4” and “YT=#3” indicate that X/Yaddresses of the initial value of an information area are respectivelystored in XT/YT. Furthermore, “IDX8=#C” specifies a number of times ofloop when a command JNI is issued. Moreover, “EXTRA WRITE=C0” typicallyspecifies that writing into the information write space is carried outby an MUT control “C0”. Additionally, “CPE=R” specifies that comparisonis performed in a cycle “R”.

(2) Execution Command pattern

START #00 JNI. X<XB Y<YB XB<XB+1 YB<YB+1{circumflex over ( )}BX R JNI.−1X<XT Y<YT YT=YT+4 C0 STPS

“START #00” in the above execution command pattern is indicative of apattern program execution start address. A command “JNI” is executed fora number of times set in an IDX register at a specified position. “.” in“JNI.” specifies the same row, and “−1” in “JNI.−1” specifies aprecedent row. Further, “STPS” is a pattern program end command (SETPASS).

Furthermore, an address of the flag “F” is set in a “C0” descriptioncycle, and the write inhibition is released.

As a result, the processing to inhibit writing information into thesecond block 42 by the bad block mask (BBM) is temporarily released.Consequently, a flag 401 (FIG. 2) can be written into the informationwrite space 42 a in which writing of information is inhibited.

<3>Third Block

A value of each signal in the third block write period is the same asthat in the first block write period, thereby omitting a detailedexplanation of the operation in this period.

<4>Fourth Block

In the fourth block, a failure cell is detected by the logic comparator5 during the test. The logic comparator 5 which has detected a failurecell outputs the fail signal S2 to the failure analysis memory 6. Thatis, a value of the fail signal S2 becomes “1”.

Moreover, the logic comparator 5 outputs the inhibit signal S3 to theoutput controller 3 by the fail loop back function in the second blockwrite period after detection of the failure cell. That is, a value ofthe *mask signal S1 becomes “1”. As a result, an output value of thefirst OR circuit 31 of the output controller 3 also becomes “1”.

Consequently, in a period that a value of the release signal S4 is “0”,an output value of the AND circuit 33 is “1”and a value of the resetsignal S5 outputted from the second OR circuit 32 is “1”. Therefore, adriver output from the flip-flop 30 is stopped, and writing ofinformation into the memory device 4 is inhibited.

In this manner, the fourth block 44 after the failure cell enters thewrite inhibit state by the fail loop back (FLB) function in a periodthat the release signal S4 is not outputted.

In this embodiment, the flag 401 indicated by “F” in FIG. 2 is writteninto the information write area 44 a of the fourth block 44 in whichwriting is inhibited. Therefore, the release signal S4 is outputted witha timing to write the flag 401. That is, a Value of the release signalis set to “1”. While a value of the release signal S4 is “1”, an outputvalue of the AND circuit 33 becomes “0”and a value of the reset signalS5 outputted from the second OR circuit 32 becomes “0”.

As a result, the processing to inhibit writing information into thefourth block 44 by the fail loop back (FLB) function is temporarilyreleased. Consequently, the flag 401 can be written into the informationwrite space 44 a in which writing is inhibited.

Since the flag can be also written into the write-inhibited block inthis manner, the information write space can be effectively utilizedeven if the back block mask function or the fail loop back function isused.

Although the description has been given as to the example that thepresent invention is constituted under the specific conditions in theforegoing embodiment, the present invention can be modified in manyways. For example, the example that the flash memory is a device undertest has been described in the above embodiment, but the memory deviceas a device under test is not restricted to the flash memory in thepresent invention.

As described above, according to the present invention, the processingto inhibit writing into the block by the bad block mask function or thefail loop back function can be released by the release signal. As aresult, even in the state that the writing into the block is inhibited,information such as a flag can be written into the information writespace of the block. As a result, a write cycle to write information inthe information write space does not have to be added, and informationcan be written especially in the fail loop back function in that cycle,thereby enabling the faster processing.

INDUSTRIAL APPLICABILITY

As described above, the semiconductor test apparatus according to thepresent invention, the processing to inhibit writing into the block bythe bad block mask function or the fail loop back function can bereleased by the release signal.

Therefore, the present invention can be optimally used as asemiconductor test apparatus which determines the memory device, e.g., aflash memory as a device under test.

1. A semiconductor test apparatus which tests as a device under test amemory device whose memory area is divided into a plurality of blocks,comprising: a pattern generation block which generates a waveformcontrol signal and an expected pattern signal as well as an addresssignal specifying a write address in the memory device; a waveformformatter/timing generator which outputs a test pattern signal whosewaveform is formatted by the waveform control signal, and also outputs awrite enable signal which enables writing of the test pattern signalinto the test memory; a logic comparator which compares an output signaloutputted from the memory device in response to the input test patternsignal with an expected pattern signal, detects a failure cell based onthe expected pattern signal and the response output signal and outputs afail signal, and also outputs an inhibit signal which instructsinhibition of writing into a memory area which is tested after thefailure cell in a block in which the failure cell is detected; a failureanalysis memory which stores the failure information at an addressindicated by the address signal, and outputs a mask signal whichinstructs inhibition of writing into a block in which a failure cell isdetected in advance; and an output controller which stops output of thewrite enable signal to the memory device when one or both of the inhibitsignal and the mask signal are inputted, wherein the pattern generationblock outputs a release signal which cancels the write inhibitinstruction based on the inhibit signal and on the mask signal, and theoutput controller outputs the write enable signal when the releasesignal is inputted even if one or both of the inhibit signal and themask signal are inputted.
 2. The semiconductor test apparatus accordingto claim 1, wherein the pattern generation block outputs the releasesignal with a timing to write information into a cell in an informationwrite space of a block that writing is inhibited by the mask signaland/or a timing to write information into a cell in a write areaincluded in an area that writing is inhibited by the inhibit signal. 3.The semiconductor test apparatus according to claim 1, wherein theoutput controller includes: an OR circuit to which the inhibit signaland the mask signal are inputted; an AND circuit to which an output ofthe OR circuit and the release signal are inputted; and a flip-flop towhich an output of the AND circuit is inputted as a reset signal and thewrite enable signal is inputted as a set signal.
 4. The semiconductortest apparatus according to claim 1, wherein the memory device is aflash memory.
 5. The semiconductor test apparatus according to claim 1,wherein the release signal is included in a memory device controlsignal.